|Intel Core 2's FSB, RAM, and Bandwidth Explained|
|Written by Icrontic|
|Monday, 21 January 2008|
Today, Icrontic serves up a crash-course in the mysterious relationship of the Core 2 front side bus, RAM and bandwidth. The nature of the Core 2's design may be baffling, particularly to users exiting the era of synchronized Athlon XP buses, and we intend to cut through the haze and serve it straight just as we like to. Before we begin, however, there is a bit of background information that we will establish so we can quickly dispense with the rest of the juicy morsels.