|DDR3 RAM: System Memory Technology Explained|
|Articles - Featured Guides|
|Written by Olin Coles|
|Sunday, 11 May 2008|
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DDR3: Prefetch Buffer
The SDRAM family has seen generations of change. JEDEC originally stepped in to define standards very early on in the production timeline, and subsequently produced DDR, DDR2 and now DDR3 DRAM (dynamic random access memory) implementations. You already know that DDR3 SDRAM is the replacement for DDR2 by virtue of its vast design improvements, but you might not know what all of those improvements actually are.
In additional to the logically progressive changes in fabrication process, there are also improvements made to the architectural design of the memory. In the last section I extolled the benefits of saving power and conserving natural resources by using DDR3 system memory, but most hardware enthusiasts are not aware of how efficiency is now also extended into a new data transfer architecture introduced fresh in DDR3.
One particularly important new change introduced with DDR3 is in the improved prefetch buffer: up from DDR2's four bits to an astounding eight bits per cycle. This translates to a full 100% increase in the prefetch payload; not just the small incremental improvement we've seen from past generations. Remember this important piece of information when I discuss CAS latency later on, because it makes all the difference.
Even in it's infancy, DDR3 offers double the standard JEDEC standard maximum speed over DDR2. According to JEDEC standard JESD 79-3B drafted on April 2008, DDR3 offers a maximum default speed of 1600 MHz compared to 800 MHz for DDR2. But this is all just ink on paper if you aren't able to actually notice an improvement in system performance.
So far, we discussed how DDR3 is going to save the average enthusiast up to 37% of their energy costs consumed by system memory. We also added a much larger 8-bit prefetch buffer to the list of compelling features. So let's cinch it all together with a real ground-breaking improvement, because DDR3 has introduced a brand new system for managing the data bandwidth bus.
Completely new to DDR3 is the 'Fly-by' technology. In the past generations of SDRAM to include DDR2, system memory used a 'Star' topology to disseminate data across many branched signal paths. This improvement is similar to when automobiles first began using the front-wheel drive system to bypass the long drivetrain linkage which incrementally sapped power from the wheels. Essentially, the Fly-by data bus topology utilizes a single direct link between all DRAM components which allows the system to respond much quicker than if it had to address stubs.
The reason DDR2 cannot develop beyond the point it already has isn't truly an issue of fabrication refinements, it is more specifically an issue with mechanical limitations. Essentially, DDR2 technology is no better prepared to reach higher speeds than a propeller airplane is capable of breaking the sound barrier; in theory it's possible, just not with the mechanical technology presently developed. At higher frequency the DIMM module becomes very dependant on signal integrity, and topology layout becomes an critical issue. For DDR2 this would mean that each of the 'T branches' in the topology must remain balanced, an effort which is beyond its physical limitation.
With DDR3 however, the signal integrity is individually tuned to each DRAM module rather than balanced across the entire memory platform. Now both the address and control line travel a single path instead of the inefficient branch pattern T topology in DDR2. Each DDR3 DRAM module also incorporates a managed leveling circuit dedicated to calibration, and it is the function of this circuit to memorize the calibration data. The Fly-by topology removes the mechanical line balancing limitations of DDR2, and replaces it with an automatic signal time delay generated by the controller fixed at the memory system training.
Although it is a rough analogy, DDR3 is very similar to the advancement of jet propulsion over prop-style aircraft, and an entirely new dimension of possibility is made available. There is a downside however, and this is primarily in the latency timings. In our next section, Benchmark Reviews will discuss how DDR3 can aid in overclocking, and why the higher latency will have little effect on the end result.